1. Field
A method of patterning a block copolymer layer and a patterned structure are disclosed.
2. Description of the Related Art
Recently, demand for lithography technology for forming a high-resolution nano-sized pattern for fabricating a semiconductor memory or a logic circuit has increased in accordance with a decrease in a size of electronic devices and an increase in an integration degree of semiconductor devices. Conventional photolithography technology have difficulties in providing a nano-sized pattern, in particular, a nano-pattern having features of less than or equal to about 20 nm due to the wavelength resolution limit. In this regard, a method of forming a higher resolution pattern using a resolution enhancement technique (“RET”) has been suggested, and research to develop optical lithography using an extreme ultraviolet (“EUV”) wavelength of 13.5 nm or non-optical patterning lithography, such as directed self-assembly lithography (hereinafter referred to as “DSA”) is ongoing.
Thus there remains a need for an improved patterning method to provide materials suitable for semiconductor fabrication.